RealWorldTech: At the MicroProcessor Forum, Dr. Brad McCredie of IBM continued to tease out particulars regarding the POWER6. The presentation discussed a lot of general microarchitecture features, but did not reveal many specific details; a full revelation of the microarchitecture will likely have to wait till ISSCC, next February. However, from the details that were revealed, it is clear that the POWER6 inherited many characteristics from its predecessors, yet made substantial improvements in others.

The POWER6 is targeted to run at 4-5GHz and was fabricated on IBM’s 65nm SOI process with 10 layers of metal. Compared to the 90nm process, there is a 30% performance increase at a given power level, largely due to the use of dual-stress line technology. IBM’s 65nm process offers a 0.65um high performance SRAM cell, and a 0.45um cell for density. The array cells use a lower supply voltage compared to the logic, to reduce power consumption. By all accounts, IBM heavily emphasized circuit design in the POWER6, as the means to increase frequency, while prior designs relied extensively on automated tools and logic design. This helps to explain how IBM was able to dramatically increase the frequency, but it is still hard to believe that such optimizations were never made previously. Leaving a 2x performance boost on the table seems unconscionable from a competitive positioning point of view.

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